ARCHITECTURAL LEVEL SUBTHRESHOLD LEAKPAGE POWER ESTIMATION OF SRAM ARRAYS WITH ITS PERIPHERALS
NAVLAKHA, NUPUR (2011PEV5148)
ARCHITECTURAL LEVEL SUBTHRESHOLD LEAKPAGE POWER ESTIMATION OF SRAM ARRAYS WITH ITS PERIPHERALS A Dissertation Report - JAIPUR DEPARTMENT OF ELECTRONIC AND COMMUNICATION ENGINEERING, MALVIYA NATIONAL INSTITUTE OF TECHNOLOGY,JAIPUR 2013 - Vp.
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI
LEAKPAGE POWER ESTIMATION OF SRAM ARRAYS WITH ITS PERIPHERALS
ARCHITECTURAL LEVEL SUBTHRESHOLD LEAKPAGE POWER ESTIMATION OF SRAM ARRAYS WITH ITS PERIPHERALS A Dissertation Report - JAIPUR DEPARTMENT OF ELECTRONIC AND COMMUNICATION ENGINEERING, MALVIYA NATIONAL INSTITUTE OF TECHNOLOGY,JAIPUR 2013 - Vp.
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI
LEAKPAGE POWER ESTIMATION OF SRAM ARRAYS WITH ITS PERIPHERALS