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Design of a New Digital PLL Frequency Synthesizer in 0.18 um CMOS Technology With Low Locking Time/Project Report edited by AGARWAL, SANJEEV

By: MEHTA, KOMAL.
Contributor(s): AGARWAL, SANJEEV.
Material type: materialTypeLabelBookPublisher: JAIPUR DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,MALVIYA NATIONAL INSTITUTE OF TECHNOLOGY,JAIPUR 2009Subject(s): PROJECT REPORT | KOMAL MEHTA | DIGITAL PLL FREQUENCY SYNTHESIZER IN 0.18 UM CMOS TECHNOLOGY | ELECTRONICS AND COMMUNICATION ENGINEERING
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Item type Current location Call number Status Date due Barcode
Project Reports Project Reports Malaviya National Institute of Technology
(Browse shelf) Available EV064

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