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LIMITS TO VOLTAGE SCALING FROM THE LOW POWER DESIGN PERSPECTIVE OF DIGITAL COMBINATORIAL CIRCUITS WITH COMPLEMENTARY CMOS LOGIC : a dissertation report

By: SINGH, ARUN KUMAR ( 0663831 )Contributor(s): AGRAWAL, SANJEEV [Supvr]Material type: Text

Text

TextPublication details: JAIPUR DEPARTMENT OF ECE, MNIT 2008 Description: Subject(s): VLSI | ELECTRONICS AND COMMUNICATION ENGINEERING | DIGITAL COMBINATORIAL CIRCUITS WITH COMPLEMENTARY CMOS LOGIC

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Item type	Current library	Call number	Status	Date due	Barcode
Dissertations	Malaviya National Institute of Technology	(Browse shelf(Opens below))	Available		PEV055

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