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Power reduction techniques for content addeessable memory : a dissertion report

By: Gangwar,EktaContributor(s): Periasamy,C [guide]Material type: Text

Text

TextPublication details: Jaipur: Deptt. of Electronic and Communication Engineering. MNIT. 2016 Description: 52pSubject(s): Electronic and Communication Engineering | Review-Addressable Memory | VLSI DesgnDDC classification: 621.38

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Item type	Current library	Call number	Status	Date due	Barcode
Dissertations	Malaviya National Institute of Technology Reference	621.38 (Browse shelf(Opens below))	Available		EV165

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Previous	621.38 Performance Analysis of Diffrent 40 Gb/s Passive Optical Network Techniques	621.38 A current feedback amplifier based approach for efficent design of low complexity universal bi-quadratic filters	621.38 Genuine and fake currency detection using image processing and edge detection of real -time image	621.38 Power reduction techniques for content addeessable memory	621.38 Performancce analyssis of two Dimensions Codes in optical code division multiple access systems:	621.38 fET implelimentatoin on Fpga using new Distributed Arithmetic with different Adders:	621.38 Design and Modeling of Diaphargm type mems based capacitive pressure sensor for harsh Envirroment:	Next

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