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Performance Estimation of Asic through Clock Tree Aware placement flow a dissertation report

By: Sharma, Neeraj Kumar (2019PEV5259)Contributor(s): Sahu, Chitrakant [Supvr ]Material type: TextTextPublication details: Jaipur Department of Electronics & Communication, MNIT 2021 Description: 58p. 01 CD availableSubject(s): Performance Estimation of Asic through Clock Tree Aware placement flow | VLSI SoC Design | Problem Statement and Objective of workDDC classification: 621.38
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