| 000 | 00570nam a22001817a 4500 | ||
|---|---|---|---|
| 003 | OSt | ||
| 005 | 20140420215808.0 | ||
| 008 | 14042 2013xxu||||| |||| 00| 0 eng d | ||
| 040 | _c | ||
| 100 | _aGODARA, JALA RAM | ||
| 245 |
_aBehavioral Modeling and Simulation of PLL ADCs and DACs using VHDL-AMS Language _cEdited by BOOLCHANDANI, D |
||
| 260 |
_aJaipur _bELECTRONICS & COMMUNICATION ENGINEERING, MNIT _c2013 |
||
| 650 | _aSIMULATION OF PLL ADCS AND DACS USING VHDL-AMS | ||
| 650 | _aVLSI | ||
| 650 | _aJALA RAM GODARA | ||
| 650 | _aPROJECT REPORT | ||
| 942 |
_2ddc _cAI |
||
| 999 |
_c59594 _d59594 |
||