000 00655nam a22001697a 4500
008 230807b |||||||| |||| 00| 0 eng d
082 _a621.38
_bSHA
100 _aSharma, Neeraj Kumar (2019PEV5259)
245 _aPerformance Estimation of Asic through Clock Tree Aware placement flow
_ba dissertation report
260 _aJaipur
_bDepartment of Electronics & Communication, MNIT
_c2021
300 _a58p.
_e01 CD available
650 _aPerformance Estimation of Asic through Clock Tree Aware placement flow
650 _aVLSI SoC Design
650 _aProblem Statement and Objective of work
700 _aSahu, Chitrakant
_eSupvr
942 _cDS
999 _c78833
_d78833