Normal view MARC view ISBD view

TEST SCHEME FOR FLASH MEMORY ARRAY USING FUNCTIONAL MODEL OF DUAL-GATE MOSFET

AGRAWAL, RENU

TEST SCHEME FOR FLASH MEMORY ARRAY USING FUNCTIONAL MODEL OF DUAL-GATE MOSFET edited by SAHULA, VINEET ; KUMAWAT, RENU - JAIPUR DEPARTMENT OF ECE, MNIT 2009

Subjects--Topical Terms:
PROJECT REPORT
RENU AGRAWAL
TEST SCHEME FOR FLASH MEMORY ARRAY
VLSI
ELECTRONICS AND COMMUNICATION ENGINEERING

Print
Add to your cart (remove)
Suggest for purchase
Save record
BIBTEX Dublin Core MARCXML MARC (non-Unicode/MARC-8) MARC (Unicode/UTF-8) MARC (Unicode/UTF-8, Standard) MODS (XML) RIS
More searches

Search for this title in:
Other Libraries (WorldCat) Other Databases (Google Scholar) Online Stores (Bookfinder.com) Open Library (openlibrary.org)

TEST SCHEME FOR FLASH MEMORY ARRAY USING FUNCTIONAL MODEL OF DUAL-GATE MOSFET

©2023 Central Library, Malaviya National Institute of Technology Jaipur