Efficient parallel architecture for optimizing performance in SoCs (Record no. 77361)

MARC details
000 -LEADER
fixed length control field 00619nam a2200169 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 230331b |||||||| |||| 00| 0 eng d
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 004
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Mitra, Ved (2013RCP9563)
245 ## - TITLE STATEMENT
Title Efficient parallel architecture for optimizing performance in SoCs
Remainder of title : a thesis report
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc. Jaipur
Name of publisher, distributor, etc. Department of Computer Science Engineering, MNIT
Date of publication, distribution, etc. 2022
300 ## - PHYSICAL DESCRIPTION
Extent xvii,89
Accompanying material +1CD
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Science Engineering
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Efficient parallel architecture for optimizing performance in SoCs
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Govil, Mahesh Chandra
Relator term Supvr.
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Singh, Girdhari
Relator term Supvr.
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Thesis
Source of classification or shelving scheme Dewey Decimal Classification
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Shelving location Date acquired Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type
    Dewey Decimal Classification     Malaviya National Institute of Technology Malaviya National Institute of Technology Reference 31/03/2023   004 TH00691 31/03/2023 31/03/2023 Thesis