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Wafer-Level Testing and During Burn-in for Integrated Circuits

By: BAHUKUDUMBI, SUDARSHANContributor(s): CHAKRABARTY, KRISHNENDUMaterial type: TextTextPublication details: London Artech House 2010 Description: xv,198pISBN: 9781596939899Subject(s): INTEGRATED CIRCUITS--WAFER-SCALE INTEGRATION | ELECTRONICS AND COMMUNICATION ENGINEERINGDDC classification: R 621.381
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Holdings
Item type Current library Call number Status Date due Barcode
REFERENCE Malaviya National Institute of Technology
R621.3815 BAH (Browse shelf(Opens below)) Not for loan 79139

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