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A spice modelling of high-performance ternary half adder design using gnrfet technology a dissertation report

By: Kalyan, Mangu Krishna (2020PEB5288)Contributor(s): Bairathi, Rakesh [Supvr. ]Material type: TextTextPublication details: Jaipur Department of Electronics & Communication, MNIT 2022 Description: 89p. 01 CD AvailableSubject(s): A spice modelling of high-performance ternary half adder design using gnrfet technology | introduction to MVL | Interpreting Ternary logic levelsDDC classification: 621.38
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