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Layout Designing and Analysis of a Programmable Asynchronous Level Converter in Low Power Dual VDD System

CHAWLA, PUNEET (036321)

Layout Designing and Analysis of a Programmable Asynchronous Level Converter in Low Power Dual VDD System A Dissertation Report - JAIPUR DEPARTMENT OF ECE, MNIT 2005 - vp.

Subjects--Topical Terms:
ASYNCHRONOUS LEVEL CONVERTER : PUNEET CHAWLA
Electrical & Communication Engineering

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Layout Designing and Analysis of a Programmable Asynchronous Level Converter in Low Power Dual VDD System

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