Layout Designing and Analysis of a Programmable Asynchronous Level Converter in Low Power Dual VDD System (Record no. 51639)

MARC details
000 -LEADER
fixed length control field 00546pam a2200145a 44500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 140414b2005 xxu||||| |||| 00| 0 eng d
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name CHAWLA, PUNEET (036321)
245 ## - TITLE STATEMENT
Title Layout Designing and Analysis of a Programmable Asynchronous Level Converter in Low Power Dual VDD System
Statement of responsibility, etc : A Dissertation Report
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc JAIPUR
Name of publisher, distributor, etc DEPARTMENT OF ECE, MNIT
Date of publication, distribution, etc 2005
300 ## - PHYSICAL DESCRIPTION
Extent vp.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element ASYNCHRONOUS LEVEL CONVERTER : PUNEET CHAWLA
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Electrical & Communication Engineering
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name BAIRATHI, RAKESH
Relator term Supvr
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Dissertations
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Total Checkouts Full call number Barcode Date last seen Koha item type
    Dewey Decimal Classification     Malaviya National Institute of Technology Malaviya National Institute of Technology 07/01/2014   PEV035 15/04/2014 Dissertations