Search

Image from Google Jackets

Normal view MARC view ISBD view

System-on-chip test architectures : nanometer design for testability / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba.

Contributor(s): Wang, Laung-Terng | Stroud, Charles E | Touba, Nur AMaterial type: Text

Text

TextSeries: The Morgan Kaufmann series in systems on siliconPublication details: Amsterdam ; Boston : Morgan Kaufmann Publishers, c2008. Description: xxxvi, 856 p. : ill. ; 25 cmISBN: 9780123739735 (hardcover : alk. paper)Subject(s): Systems on a chip -- Testing | Integrated circuits -- Very large scale integration -- Testing | Integrated circuits -- Very large scale integration -- DesignDDC classification: 621.395

Average rating: 0.0 (0 votes)

Holdings ( 1 )
Title notes ( 1 )
Comments ( 0 )

Holdings
Item type	Current library	Call number	Status	Date due	Barcode
REFERENCE	Malaviya National Institute of Technology Reference	621.395 (Browse shelf(Opens below))	Not for loan		73568

Browsing Malaviya National Institute of Technology shelves, Shelving location: Reference Close shelf browser (Hides shelf browser)

Previous	No cover image available	No cover image available	No cover image available		No cover image available	No cover image available	No cover image available	Next
Previous	621.392 SIN PERFORMANCE EVALUATION OF ROUTING PROTOCOLS IN MOBILE AD HOC NETWORKS (MANETs)	621.392 TIW POSITION VALIDATION FOR IDENTIFICATION OF MALICIOUS VEHICLES IN VANETs	621.395 DESIGN OF LONG RANG WIRELESS STREET LIGHT CONTROL SYSTEM	621.395 System-on-chip test architectures :	621.395 AGR Hardware Implementation Of Binary LDPC Encoder	621.395 AGR Design and analysis of low voltage high speed double tall comparator :	621.395 AGR Scalability analysis and performance comparison of junctionless thin film transistors:	Next

Includes bibliographical references and index.

There are no comments on this title.

to post a comment.

Share

©2023 Central Library, Malaviya National Institute of Technology Jaipur